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ADE7758
REGISTERS
COMMUNICATIONS REGISTER
The communications register is an 8-bit, write-only register that
controls the serial data transfer between the ADE7758 and the
host processor. All data transfer operations must begin with a
write to the communications register.
Table 16. Communications Register
Data Sheet
The data written to the communications register determines
whether the next operation is a read or a write and which
register is being accessed.
Table 16 outlines the bit designations for the communications
register.
Bit Location
0 to 6
7
Bit Mnemonic
A0 to A6
W/R
Description
The seven LSBs of the communications register specify the register for the data transfer operation.
Table 17 lists the address of each ADE7758 on-chip register.
When this bit is a Logic 1, the data transfer operation immediately following the write to the
communications register is interpreted as a write to the ADE7758 . When this bit is a Logic 0, the data
transfer operation immediately following the write to the communications register is interpreted as a
read operation.
DB7
W/R
DB6
A6
DB5
A5
DB4
A4
DB3
A3
DB2
A2
DB1
A1
DB0
A0
Table 17. ADE7758 Register List
Address
Default
[A6:A0]
Name
R/W 1
Length
Type 2
Value
Description
0x00
Reserved
–
Reserved.
0x01
AWATTHR
R
16
S
0
Watt-Hour Accumulation Register for Phase A. Active power is
accumulated over time in this read-only register. The AWATTHR register
can hold a maximum of 0.52 seconds of active energy information with
full-scale analog inputs before it overflows (see the Active Energy
Calculation section). Bit 0 and Bit 1 of the COMPMODE register determine
how the active energy is processed from the six analog inputs.
0x02
0x03
0x04
BWATTHR
CWATTHR
AVARHR
R
R
R
16
16
16
S
S
S
0
0
0
Watt-Hour Accumulation Register for Phase B.
Watt-Hour Accumulation Register for Phase C.
VAR-Hour Accumulation Register for Phase A. Reactive power is
accumulated over time in this read-only register. The AVARHR register
can hold a maximum of 0.52 seconds of reactive energy information
with full-scale analog inputs before it overflows (see the Reactive Energy
Calculation section). Bit 0 and Bit 1 of the COMPMODE register
determine how the reactive energy is processed from the six analog
inputs.
0x05
0x06
0x07
BVARHR
CVARHR
AVAHR
R
R
R
16
16
16
S
S
S
0
0
0
VAR-Hour Accumulation Register for Phase B.
VAR-Hour Accumulation Register for Phase C.
VA-Hour Accumulation Register for Phase A. Apparent power is
accumulated over time in this read-only register. The AVAHR register can
hold a maximum of 1.15 seconds of apparent energy information with
full-scale analog inputs before it overflows (see the Apparent Energy
Calculation section). Bit 0 and Bit 1 of the COMPMODE register determine
how the apparent energy is processed from the six analog inputs.
0x08
0x09
0x0A
BVAHR
CVAHR
AIRMS
R
R
R
16
16
24
S
S
S
0
0
0
VA-Hour Accumulation Register for Phase B.
VA-Hour Accumulation Register for Phase C.
Phase A Current Channel RMS Register. The register contains the rms
component of the Phase A input of the current channel. The source is
selected by data bits in the mode register.
0x0B
0x0C
0x0D
BIRMS
CIRMS
AVRMS
R
R
R
24
24
24
S
S
S
0
0
0
Phase B Current Channel RMS Register.
Phase C Current Channel RMS Register.
Phase A Voltage Channel RMS Register.
Rev. E | Page 60 of 72
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